In this tutorial we see how to create project in KEIL MDK uVision 5 for STM32 ARM Cortex-M based MCUs. Its for beginners who want to get started in programming STM32 with Keil. This tutorial also applies for all supported devices across the STM32 Family viz. STM32F0/F1/F2/F4/F7/etc/. Keil uV 5 is much different than older Keil uV4. uVision 5 has integrated pack installer which is used to install specific MCU family packs and other libraries. To create project for STM32 MCU, you will first need to install MDK5 software packs for your microcontroller family. Either you can download it separately or do it from within the IDE.I recommend adding software packs using IDE.

Basically three(or more?) types of STM32 Keil projects can be created:

1. One that uses CMSIS(core) only.
2. One that is based on Standard Peripheral Library.
3. Finally, one that is based on HAL (Hardware abstraction Layer) Library.

For the sake of this tutorial we will see how to create CMSIS and SPL based STM32F103C8 Keil uv5 project, as an example, but will work exactly the same for STM32F0, STM32F4, and other families. I will cover HAL based projects in another tutorial.

1) Installing prerequisite STM32 Keil software pack

If already installed, you can SKIP this.

Step A. Download latest Keil MDK uVision5 from Keil’s website.

Step B. Install Keil uVision 5 to default path.

STEP C. Open Keil 5 and click on “Pack Installer” icon as shown below:

STEP D. On the left half on the window, under “Devices” type “STM3F103C8”
(or other device name depending on the device present on your development board) in search box and select the MCU in the list below. Now, on the right half of the window click on the “install” button which is towards to the right of “Keil:STM32F1xxx_DFP” and “Keil:STM32NUCLEO_B”. Repeat this step if want to add support for other device family. After this, wait until pack installer finishes downloading the required pack files for selected MCU.

Alternatively, you can manually download the software pack and install it directly from MDK5 Software Packs. It will be present Under “KEIL-> STMicroelectronics STM32F1 Series Device Support, Drivers”. In general for STM32Fx Devices.

STEP E. After installing from Pack Installer you will get a confirmation to reload packs. Click “Yes” as shown below:

2) Step by step Tutorial

Okay, so now we have the necessary packs installed to create our first STM32 project in Keil 5. Just follow the steps mentioned below to create a new project in Keil uV 5 or if your project is not working properly:

Step 1.

Open the Keil IDE, under main menu goto “Project->New uVision Project…” and a window prompt will open asking to save the new project. Type your desired project name and save.

Step 2.

After that, a new window will appear as shown below. Make sure “Software Packs” is selected for the 1st drop down. In the search box below it, type “STM32F103C8” and then select the device from list below. For e.g.: STM32F103C8 for STM32 Blue Pill, STM32F103RB for Nucleo-F103RB, STM32F030R8 for Nucleo-F030R8 and so on.

Finally click “OK”.

Step 3.

A. For CMSIS:
Inside the “Manage Run-Time Environment Window” select the check boxes for “CORE” under “CMSIS” and “Startup” under “Device”. If you want to select any other libraries you can do so by selecting the respective checkboxes. Selecting “Startup” will automatically add all the necessary startup/boot files required for STM32F1xx device, so we don’t have to import them from external sources. The selection of libraries can be changed any time later.

B. For Standard Peripheral Library (SPL):
If you want to use SPL, the select the required peripheral library components as required. Note that some components have dependencies as well, so you will also need to include dependent components. For. E.g. GPIO needs RCC to enable clocks.

Step 4.

Now click on “Options for Target” button as shown below:

Make sure the settings match as shown below.

Step 5.

Now, click on the “Output” tab. If you want to generate hex file then you can check “Create HEX File”. You also enter a suitable name for the executable output file.

Step 6.

Then click on the “Linker” tab and Under that tab check the checkbox option which says “Use Memory Layout from Target Dialog”.

Step 7.

Now, under the “Debug” tab, select ST-LINK as debugger since its the most common for debugging and programming STM32. Finally to click “OK” to apply settings and close window.

Step 8.

Now, in the source navigation pane on the left area, right click on “Source Group 1” and select “Add New Item to Group ‘Source Group 1′”.

Step 9.

A new window will pop-up to add an item as shown below. Select “C File (.c)” or C++ File (.cpp) , then enter the name of the file in the text box to the right of “Name:” and click “Add”.

Step 10.

Now you can write your code in the editor. To compile your program Press “F7” key or in the main menu goto “Project->Build Target”. To check for any compilation errors you can have a look at the build output at the bottom of main window. Two screenshots of the Keil MDK uVision 5 are given below.

A. For CMSIS Core Project:

B. For Standard Peripheral Library based Project:

The post Create new STM32 project in Keil uVision 5 tutorial appeared first on OCFreaks!.

Here, IRPn represents nth Interrupt Priority Register. PRI_m is the Priority field for Interrupt m (IRQm).

• The IPR number n for Interrupt m is the Quotient of “m/4” i.e. n = (int)m/4 = m DIV 4
• The byte offset is the remainder of “m/4” i.e. offset = m % 4 = m MOD 4

In Cortex-M3, each of these fields can be further sub-divided into two parts, which are:

• Preemption Priority or Group Priority level: This is upper part(sub-field) of the 8-bit priority field. This is the main priority level which defines the preemption of interrupt exceptions or IRQs. An Interrupt will preempt the execution of the current Interrupt, if its Group Priority is higher than the Interrupt being currently serviced. Lower priority values denote higher priority & vice-versa.
• Sub-Priority Level: This comes into picture when there are multiple pending interrupts having same preemption or Group Priority. In this case the sub-priority will determine which Interrupt gets executed first. Also note that, if pending ISRs have same Group and Sub-Group priority then the Interrupt having the lowest IRQ number will be executed first.

Cortex-M0 Processor only implements 2 bits in the priority field [7:6] and rest bits [5:0] are always treated as Zeros, thereby supporting only 4 unique priority levels. This implementation is fixed for all MCUs which use Cortex-M0 (ARMv6-M) CPU. It also doesn’t implement Interrupt Priority Grouping.

Interrupt Priority Groups in ARM Cortex-M3

Based on the sub-divisions, priority groups are formed depending on how many bits are used for preemption and sub-priority levels. The master table which assigns a Priority Grouping Number for each of the 8 possible divisions is shown below:

This Priority Grouping is common for all ARM Cortex-M3 processor based microcontrollers. Any of the 8 possible grouping can be selected using the PRIGROUP field (bits[10:8]) of the AIRCR (Application Interrupt and Reset Control Register). The Priority Grouping Number value shown in the table is assigned to the PRIGROUP field of AIRCR.

For MCUs which implement less than 8 bits, the non-implemented bits are treated as Zeros in the table above. For example LPC17xx devices (like LPC1768/LPC1769) implement only 5 bits for Priority. The remaining(lower) 3 bits are treated as Zeros. This is shown below:

LPC176x Interrupt Priority Grouping

An Example with Priority Grouping of 5 on LPC17xx Devices which implement 5 bits for Priority is as follows:

STM32 (STM32F10xxx) Interrupt Priority Grouping

Priority Grouping for other Cortex-M3 MCUs from the STM32 family like STM32F103, etc.. which implement only 4 bits of interrupt priority is given below.

Similarly we can get the Priority Grouping table for LPC13xx devices like LPC1343/LPC1347 using the master table. Note that LPC134x MCUs implement only 3 bits of Priority hence can give 8 unique priority levels.

PRIGROUP can get a bit confusing since the unimplemented bits are towards the LSb i.e. in the lower half starting from bit location 0. But thankfully all of this hassle is handled by the CMSIS library.

Assigning/Programming Priority Levels using CMSIS

The CMSIS NVIC functions defined in core_cm3.h header defines standard interfaces for Configuring and Assigning Interrupt Priority levels which are listed below. These functions take care of aligning the priority bits as required, if the number of implemented bits are less than 8. First lets see the declarations of these functions.

void NVIC_SetPriorityGrouping(uint32_t PriorityGroup);

uint32_t NVIC_GetPriorityGrouping(void);

uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority);

void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);

void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);

uint32_t NVIC_GetPriority(IRQn_Type IRQn);

• NVIC_SetPriorityGrouping(): This function is used to select the Priority Grouping. The parameter PriorityGroup is the Priority Grouping Number as given the Tables above. This function changes the PRIGROUP bits[10:8] of AIRCR(Application Interrupt & Reset Control Register) register which defines how the Priority Fields in IPRs are split.
• NVIC_GetPriorityGrouping(): It returns the Priority Grouping(0 to 7) currently selected.
• NVIC_EncodePriority(..): This function will return “encoded” Priority Field for given a Priority Grouping(0 to 7), Preempt Priority and Sub-Priority. This function automatically takes care of un-implemented bits. The value returned by this function can be directly assigned to required Priority field in IPRn using NVIC_SetPriority(..).
• NVIC_DecodePriority(..): This function will “decode” the Priority Field into Pre-empt Priority and Sub-Priority for a given Priority Grouping(0 to 7).
• NVIC_SetPriority(..): As the name suggestes, it is used to assign a priority for given Interrupt source. Note that the parameter priority must be in accordance with Priority Grouping selected, hence NVIC_EncodePriority() must be used to encode priority before calling this function.
• NVIC_GetPriority(..): Returns the priority value for given IRQ.

C/C++ Example 1:

#include <lpc17xx.h>

int main(void)
{
	unsigned int priority = 0;
	
	NVIC_SetPriorityGrouping(4); 
	/* bits[7:5] used for Group Priority
	   bits[4:3] used for Sub-Group Priority */
	
	priority = NVIC_EncodePriority(4,2,0);
	/*4= Priority Grouping, 2= Group Priority, 0= Sub-Priority*/

	NVIC_SetPriority(TIMER0_IRQn,priority); //Set new Priority
	
	while(1)
	{
		/*Code.*/
	}
	
	//return 0;
}

C/C++ Example 2:

#include <lpc17xx.h>
#define NUM_IRQn 35 //Total number of peripheral interrupts
#define PRIGROUP_4 4
#define DEFAULT_GROUP_PRI 7
#define DEFAULT_SUB_PRI 3
#define TIMER2_GROUP_PRI 2
#define TIMER2_SUB_PRI 0

int main(void)
{
	unsigned int priority = 0, priGroup = 0;
	
	NVIC_SetPriorityGrouping(PRIGROUP_4); 
	/* bits[7:5] used for Group Priority
	   bits[4:3] used for Sub-Group Priority */
	
	priGroup = NVIC_GetPriorityGrouping();
	
	priority = NVIC_EncodePriority(priGroup, //=4
							DEFAULT_GROUP_PRI, //=7, Preempt/Group Priority
							DEFAULT_SUB_PRI); //=3, SubPriority within Group
	
	for(int currIRQ = 0; currIRQ < NUM_IRQn; currIRQ++ )
	{
		NVIC_SetPriority(currIRQ, priority); //Set new default Priorities for all peripheral IRQs
	}
	
	priority = NVIC_EncodePriority(priGroup, //=4
							TIMER2_GROUP_PRI, //=2, Preempt/Group Priority
							TIMER2_SUB_PRI); //=0, SubPriority within Group
	
	NVIC_SetPriority(TIMER2_IRQn, priority); //Set new higher priority for TIMER2 IRQ	
	
	while(1)
	{
		/*Code.*/
	}
	
	//return 0;
}

Exception Mask Registers

ARM Cortex-M3 implements three Exception Mask Registers which are used to disable the execution of certain group or type of Interrupts/Exceptions where they can impact the performance of time critical tasks. This is more useful for applications having real time constraints, where the system has to gurantee completion of certain tasks within required time-frame. These registers can be only accessed via core register access functions provided by CMSIS which are defined in core_cmFunc.h.

PRIMASK - Priority Mask Register

PRIMASK register is used to disable interrupts which have configurable priority i.e. External/Peripheral Interrupts when bit[0] in this register is set to 1. When set to 0 this register won't have any effect on interrupts. Rest of the bits[31:1] are reserved.

CMSIS provides 2 functions to access this register viz:

FAULTMASK - FAULT Mask Register

FAULTMASK register is used to disable all interrupts execpt Non-Maskable Interrupt(NMI) when bit[0] in this register is set to 1. When set to 0 this register won't have any effect on interrupts. Rest of the bits[31:1] are reserved.

CMSIS provides 2 functions to access FAULTMASK register viz:

BASEPRI - Base Priority Mask Register

BASEPRI register defines the minimum priority to service interrupts. Only Bits[7:0] are used. This 8-bit field is same as the priority field in IPRs. When a certain non-zero 8-bit priority value is set to this register, then it will disable all interrupts having same or lower priority than the value set. If this register is set to 0 then it won't have any effect. Note that this function doesn't shift the priority bits in case some bits are not implemented. The user is responsible for left shifiting the bits by (8 - __NVIC_PRIO_BITS) where __NVIC_PRIO_BITS is number of implemented priority bits which is defined in the device header file.

CMSIS provides 2 functions to access BASEPRI register viz:

References and Further Reading:

1. ARM Cortex-M3 User Guide
2. ARM Cortex-M3 Processor Technical Reference Manual
3. ARM Cortex-M0 User Guide
4. CMSIS-Core v5 Documentation
5. LPC176x/5x User Manual
6. STM32F10x User Manual
7. LPC13xx User Manual

The post Interrupt Priority Grouping in ARM Cortex-M NVIC appeared first on OCFreaks!.

After getting your Cortex-M development board now its time for getting started with MCUXpresso IDE. In this Step by Step tutorial we will go through how to create projects in MCUXpresso IDE for Cortex-M series Microcontrollers by NXP(Founded by Philips) based on CMSIS (Cortex Microcontroller Software Interface Standard). MCUXpresso is a derivative of LPCXpresso and Kinetis Design Studio IDEs with combined support for LCP and Kinetis MCUs. The IDE comes with integrated arm-gcc compiler and all the necessary debug drivers like LPC-Link, etc.. to get started with rapid embedded systems application development using your Xpresso board. Both older and newer boards are supported.

This guide is applicable for NXP’s Cortex-M MCU families like LPC800(e.g. LPC81x), LPC1100(e.g. LPC111x), LPC1300(e.g. LPC134x), LPC1700(e.g. LPC176x), LPC4300, etc. After creating MCUXpresso projects with CMSIS, the IDE will automatically add all the necessary startup files(for initializing MCU), headers and a project source file(C/C++) depending on the settings we choose while creating project.

Where to download the IDE from? You can download and install the IDE from the links given below:

• MCUXpresso v10.0.2
• You can always check the latest version @ MCUXpresso Software and Tools for ARM® Cortex®-M cores

After download, install from the setup file using default settings. During installation it will also install debug probe drivers which is also used to flash the code. Just click Yes/Next/Accept if its asks for driver install confirmation. By default the IDE will install to location – C:\NXP\MCUXpressoIDE_<version>\. After install follow the steps below to create a new project. In this guide I have shown project creation using LPC1114/302 as target, as an example/demo. The steps will be same for other Cortex-M series MCUs like say LPC1769. I have provided workspace archives containing example projects for LPC812, LPC1114, LPC1343 and LPC1768/LPC1769. Download links are given towards the end of this tutorial.

Step by Step Tutorial

Step 1: When you start MCUXpresso, it will first ask for a path to create a workspace. A workspace is like a master directory with settings and can contain many individual projects, more like a general “Projects” folder. When prompted enter the path where you want to create your workspace:

Step 2: Now, the IDE will launch as shown below. Now click the on “New project…” in the bottom right view of the IDE, under “Quickstart Panel” tab:

Step 3: A wizard to create a project will open. First we have to select the target MCU which we are using, from the MCU list which can be found under “Preinstalled MCUs” as shown below:

Step 4: Next select “C++ Project”:

Step 5: Next enter a suitable name for your project. Make sure that the checkbox “Use default location” is selected. This will create the project directory inside the workspace directory. Then click “Next”:

Step 6: Click on “Import” so we can import the CMSIS files for our MCU:

A new “Import…” window will appear. Click on “Browse” under “Project archive (zip)”. Then Select the required CMSIS library zip file for your MCU family. This can be found under “ide\Examples\Legacy\NXP\LPC1000”(for LPC1000 MCUs) inside the MCUXpresso installation directory and click “Next” as shown below:

select the CMSIS_CORE project only if you won’t be using CMSIS_DSPLIB or you can select both Then click on “Finish” as shown below:

Step 7: Now under “CMSIS Core library” select CMSIS_CORE_LPCxxxx for your MCU family and click Next. In the next screen, do the same for CMSIS_DSP library if you had selected it in step 6. Or select “none” and click next.

On the next options page click “Finish”:

Step 8: The IDE will now create a project with the settings we selected as shown below. The name of the source file containing the main() function will be <Project-Name>.cpp. When you are ready with your program you can click “Build” under “Quickstart Panel” to compile.

Finally, to start debugging(or Flashing compiled program) connect you Xpresso board to your computer and click on “Debug” under “Quickstart Panel”. This will start a debug session and a new pop-will appear to select your debugger(debug probe). It will automatically detect the debug probe. Just click “Next”:

Once the program is flashed on to the chip you can click on the resume(Green Triangular Play button) or F8 key to start debugging or code execution on the target MCU as shown below:

To stop debug session click on the Terminate(red square) button or “Ctrl+F2”:

Download MCUXpresso Workspace containing example/demo project and CMSIS library as zip:

• lpc81x_WS.zip – contains project for LPC812 as Target MCU
• lpc111x_WS.zip – contains project for LPC1114/302 as Target MCU
• lpc134x_WS.zip – contains project for LPC1343 as Target MCU
• lpc176x_WS.zip – contains projects for LPC1769 & LPC1768 as Target MCU

Reference(s), further reading and Resources:

• MCUXpresso IDE User Guide
• MCUXpresso Software and Tools for ARM® Cortex®-M cores
• CMSIS Overview & Components
• CMSIS-Core Documentation
• CMSIS-DAP (Debug Access port) Documentation

The post Tutorial on Using MCUXpresso to create Cortex-M projects with CMSIS appeared first on OCFreaks!.

Hi folks. In this step-by-step tutorial, I will show you how to compress videos using the free open-source tool Handbrake. This can prove especially useful to those who want to store lots of videos in devices with a limited storage capacity. Storing uncompressed large video files on such a device isn’t logical and is IMHO, downright stupid. This tutorial will get you acquainted with Handbrake and how you can use it to reduce the file size of large videos in a few minutes. You can download Handbrake from here. The detailed explanation of all the settings used in this tutorial can be found in my other articles on Handbrake(Links given at the bottom).

Without further ado, lets get started:

Step 1: Open Handbrake

Step 2: Importing Source File(s)

Import your video files to transcode by either dragging and dropping the file or clicking on “File” and navigating to the desired path. To batch encode all videos in a particular folder, click on “Folder” and navigate to the desired path. Select “MP4” container.

Handbrake Drag and Drop File

Handbrake File Open

Handbrake Folder Open

• 
• 
• 

Step 3: Picture Settings

In the Picture tab:

1. Select Anamorphic “Loose” and Modulus “2”.
2. Choose your desired Video Width. For mobile devices, I recommend a max resolution of 720p, which translates to a width of 1280 pixels for my input file (big_buck_bunny_1080p_h264.mp4).
3. Check Cropping “Custom” and make all values 0, if you don’t wish to crop your video. Or check “Automatic”, whichever works for you.

Step 4: Filter Settings

In the Filters Tab:

1. Select “NLMeans” Denoise with preset “Ultralight” and Tune “None”.

Step 5: Video Settings

In the Video Tab:

1. Select Codec “x264”, Framerate “Same as Source” and check “Variable Framerate”.
2. Check “Constant Quality” and keep the RF Slider between 21-25, no more, no less. I recommend using 24 for mobile devices.
3. Keep Encoder Preset Slider to “Veryfast”, and select Encoder Tune “Film”, Encoder Profile “Main” and Encoder Level “4.0”.

Step 6: Audio Settings

In the Audio Tab:

1. Select Codec “AAC (avcodec)”, select “Bitrate” and keep it to 160 or lower for mobile devices.

Step 6: Adding Subtitles

In the Subtitles Tab:

1. Add or remove Subtitles as per your wish.

Step 7: Finally, click on “Start Encode”

Step 7.1 (Optional): Get some coffee while your CPU does all the heavy lifting and compresses your video files & converts it to MP4 format!

For a more comprehensive, detailed and in-depth explanation of all the Handbrake settings, visit the following links:

• Handbrake Complete Tutorial Part 1: How to Transcode & Compress Videos
• Beginners Guide to Video Redundancies
• Handbrake Tutorial Part 2: x264 Advanced Encoding & Compression Settings Guide

The post How to Compress Video Files without much Quality Loss using Handbrake appeared first on OCFreaks!.

Some of you might find it odd that I made a separate post to talk about the settings in the Advanced tab of Handbrake. But rest assured, there’s a damn good reason why I chose to do so. The first tutorial was targeted at beginners. In essence, I’d say that the first tutorial was 80% handbrake and 20% some general info about videos and encoding. This tutorial would be about 20% Handbrake and 80% x264 video encoding and compression, as you need to know a fair bit about how x264 encodes video to completely understand the options in this tab.

Before going any further, let me make this clear; most users won’t need to mess around with these settings. The settings in this tab are just for those few users who like to tweak and fine tune the encoder’s settings for the video. You can get a decent output without using this tab.

x264 Video Encoding

x264 is, as of now, the most popular and widely regarded as the best video encoder out there. No other encoder comes close to it in terms of quality at a given bitrate, and it is compatible with most devices too. Let us see now what it is that makes this codec so good.

Eliminating Redundancies

To those who dont know the various redundancies that exist in a video and why eliminating them is important, check out: Video Redundancies .

To eliminate spatial and temporal redundancies, each macroblock in a frame is scanned first to identify the redundant information. These redundant information are then predicted by using various algorithms and are replaced by the “predicted” blocks, which ultimately results in a much smaller file size. Two kinds of prediction are used by x264 to predict the macroblocks in a frame:

H.264 standard defines 3 types of frames that can be used by the codec. These are:

The way the encoder arranges these frames together is called GOP(Group Of Pictures), starting with the I frame at the beginning. This, in turn is made up of mini GOPs beginning with a P/B frame. Now, consider an I frame to be of size x, a P frame 0.5x, and B frame 0.25x. For the following GOPs:

IIII: Size=4x
IPPP: Size=2.5x
IBBP: Size=2x

The advantages of using predicted frames are quite evident from the above example.

Once the predicted frames are formed (by either Intra or Inter prediction), each block in it is subtracted from the ones in the actual frame to form the residual block. These residual blocks are then transformed using either order 4 or order 8 integer transform to output a stream of coefficients for each block. The transformed coefficients are then quantized, ie, scaled by a value obtained from the Quantization Parameter(QP). The basic idea is to reduce the value of the coefficient as much as possible. The QP defines by what extent each block is to be compressed. Higher QP values mean more compression but lower quality, and lower values mean less compression but higher quality. The quantized blocks are then entropy coded to finally obtain the output video file. This is a form of lossless compression method that is done at the end, to eliminate the coding redundancies.

Rate Factor vs Quantization Parameter

One difference that you can observe when encoding videos (in Handbrake) using x264 in Constant Quality mode is that; while all other codecs will offer you a QP (Quantization Parameter) Slider, x264(and x265) will offer you an RF (Rate Factor) Slider. There is quite an inherent difference between the two.

Constant Quality encoding can be achieved by two ways:

So, which of these is better? Obviously CRF, as it can distribute bits in a much more efficient way than CQP.

Advanced Tab

The settings within this tab are unlocked by checking the “Use Advanced Tab instead” option in the Video tab. These settings allow you to fine tune your video by adjusting the various conversion parameters of the x264 codec. This tab is further subdivided into three sections: Encoding, Analysis, and Psychovisual.

Handbrake Advanced Tab

Encoding

The Encoding section deals with video compression. It offers various ways by which your video bitrate could be further reduced.

Reference Frames:

This setting specifies the maximum number of frames each P frame can use as a reference. The higher this value, the better the compression. But it must be noted that many devices have limitations on the maximum number of reference frames that can be used. So, unless your sure what this value is, keep it at default(3).

Maximum B frames:

This setting allows you to set the maximum number of successive B frames that can be encoded, after which an I or P frame has to follow for reference.

Pyramidal B frames:

Enabling this setting allows the B frames to be used as reference for other B frames wherever possible, thereby increasing compression. Options of None, Normal and Strict are provided.

• None: B frames are not used as reference.
• Strict: One B frame per mini GOP can be used as reference
• Normal: Numerous B frames per mini GOP can be used as reference.

Weighted P Frames:

Enabling this option allows the encoder to detect fades in reference frames, and assign it a particular weight. If this is OFF, the encoder will be unable to see the similarity between frames in cases where a frame is simply lighter or darker from the previous frame, as the entire frame is changing. Turning this ON can improve compression in such cases.

8×8 Transform:

Enabling this option allows the use of 8×8 blocks, rather than the normal 16×16 blocks, for prediction. This can improve compression by quite a lot(at least 5%).

CABAC:

After quantization, the data stream has to be encoded. x264 offers two methods to achieve this: CABAC(Context Adaptive Binary Arithmetic Coding) and CAVLC(Context Adaptive Variable Length Coding). CABAC offers better compression, but requires more processing power to encode and decode than CAVLC. CAVLC, on the other hand, offers inferior compression, but requires less processing power to encode and decode than CABAC.

To turn ON CABAC encoding, tick the “CABAC” checkbox. Unchecking it will use CAVLC encoding, by default.

Analysis

This section contains settings using which you can control how x264 analyzes the source video.

Adaptive B frames:

Using the options in this setting, you can control how x264 makes the decision to use a B frame.

• OFF: B frames will be placed in a fixed pattern.
• Fast: x264 can decide how many B frames to use depending on the complexity of the scene, but the decisions made are suboptimal.
• Optimal: x264 makes an optimal decision on when B frames are to be used. When using a higher number of Maximum B frames with Pyramidal B Frames, it is recommended to use this setting.

Adaptive Direct Mode:

This setting specifies how motion vectors are calculated for each block. Calculating motion vectors for every block is a CPU intensive and time consuming process. x264 has a few tricks up it’s sleeve for this.

• None: Adaptive Direct Mode is disabled. Motion Vectors have to be calculated for each block.
• Spatial: Motion vectors from the neighbouring blocks are used for the current block. This can significantly reduce the encoding time.
• Temporal: The current block is compared with the matched block in a P frame within the GOP. Using this, the motion vector is estimated rather than calculating it for each block.
• Automatic: x264 automatically chooses whether to use Spatial or Temporal for each block.

Subpixel Motion Est(subme):

One of the things that make x264 far superior to other codecs is it’s amazing Motion Compensation capabilities. x264 even supports estimating the motion of a block by a non integer number of pixels, which is called Subpixel Motion Estimation. The advantages that this offers are quite obvious.

• SAD(Sum of Absolute Differences): In this, the absolute differences between the pixels in the current block and the corresponding pixels in the block to be compared are taken, and are then added to obtain an SAD value. The block which gives the lowest SAD value will be the considered to be the block using which the motion vector will be calculated. This method can be used either with no Subpixel Motion Estimation(subme 0), or with one iteration of Quarter Pixel precision(subme 1).
• SATD (Sum of Absolute Transformed Differences):Similar to SAD, with the only difference being that the differences of each pixel is frequency transformed before being added. Although this is much slower than SAD, it gives a much better prediction. This method can be used with two iterations of Quarter Pixel precision(subme 2), one iteration of Half Pixel precision interpolated to give quarter pixel precision(subme 3), always with Quarter Pixel precision(subme 4) and with Quarter Pixel precision + Bidirectional Motion Estimation(subme 5).
• RD(Rate Distortion): The disadvantage of using SAD/SATD is that, many a time, the number of bits used for representing a sample would be more than what is actually needed. This could drastically increase the output file size, especially when using Quarter Pixel Precision.
  RD rectifies this issue by measuring the distortion D and the the number of bits R required for each decision, and comparing these with a cost function to make the mode decision. This can be used in either I/P frames(subme 6) or in all frames(subme 7).
• RD Refine: In this setting, RD is used to refine both motion vectors and mode decisions. This again, can be used in either I/P frames(subme 8) or in all frames(subme 9). This is slower than normal RD, but more efficient.
• QPRD(Quarter Pixel Rate Distortion): This setting does an RD optimization on some quarter pixels using a hexagonal search(subme 10). First, the SATD is checked. If this is found to be above the threshold value, then the RD process is skipped. If the SATD is below the threshold value, then RD is used. This process much slower, and requires trellis to be set at 2 and Adaptive Quant Strength > 0.

Motion Est Method:

x264 has a variety of search patterns for estimating how each block of pixels have moved in successive frames.

Motion Est Range(merange):

This value specifies the maximum range in pixels that the encoder searches for a match. For Diamond and Hexagon pattern, this value ranges from 4-16. For Uneven Multi Hexagon and Exhaustive, this value can be extended beyond 16, which can be particularly useful for high motion scenes.

Partition Type:

Each macroblock is broken down to form prediction blocks by the x264 encoder. There are 6 possible ways by which this can be done;

• Intra Macroblock: 16×16, 8×8
• Inter Macroblock: 16×16, 16×8, 8×16, 8×8
• The 8×8 blocks can further be broken down into even smaller blocks.

Each of these partitions are then represented using separate motion vectors. This partitioning is called mode.

A macroblock with less partitions would require lesser motion vectors to represent its motion. However, these motion vectors might not accurately represent the motion, resulting in a large error and hence encoding the error would require more bits. Similarly, more partitions would require more motion vectors to represent the motion information and fewer bits to encode the residual error.

The mode selection for each macroblock is one of the steps which contributes to x264s ability to give a great quality output at a low bitrate, but it is a time consuming process, especially if more macroblocks are partitioned.

By using the options in this setting, you can control how many macroblocks the encoder will partition. Options of Most, None ,Some and All are provided.

Trellis:

Enabling this setting allows x264 to use trellis quantization algorithm for rounding off the transformed coefficients, which can improve compression by a bit. CABAC must be enabled to use this. You can choose to use this either for encoding only or always(for both analysis and encoding). Choosing always can hit your encoding speed.

Psychovisual

Using the settings in this section, you can control the extent to which the encoder will remove psychovisual redundancies.

No DCT Decimate:

DCT Decimation allows the x264 encoder to skip encoding any of the blocks which it views as redundant information. These blocks are the not written to the output file, effectively reducing the bitrate. Checking this option will prevent x264 from skipping such blocks. This is useful if you want to preserve the grain in your videos, which are otherwise removed by DCT decimation.

Adaptive Quant Strength:

Adaptive Quantization is the process of using a different value quantizer for each block. As x264 uses CRF for constant quality(in Handbrake), this setting can be used to control how x264 distributes bits between the flat areas and the complex areas in the frames.

Higher values(>1) means more bits are allocated to the flats than to the complex areas in a frame, effectively reducing the banding artifacts, but causing some ringing artifacts. Lower Values(<1) means more bits are allocated to the edges in a frame, effectively reducing the ringing artifacts, but causing some banding artifacts.

Ringing Artifacts: In the edges of the circle.
Banding Artifacts: Discontinuities in the Gradient inside the circle and in the background.

Psychovisual Rate Distortion:

This setting adjusts the tradeoff between detail retention and actual video quality(the way the computer sees it). Higher values tend to retain the finer details(grain) at the expense of some loss in quality(undesirable blocking artifacts). The encoded video will thus, appear sharper and more detailed as compared to what it would have been if this was set to 0. To use this, subme should be 6 or higher.

Psychovisual Trellis:

This setting can be used to improve the sharpness and retain details by varying the strength function of the trellis quantization algorithm. The slider works similar to the Rate Distortion Slider. Higher values bias the finer details over the quality.

Deblocking:

Does the same thing as the Deblocking Filter in the “Filters” tab, but in a much better way. There are two parameters that you could give as input to x264’s deblocking filter: Alpha and Beta. Alpha value control the amount of deblocking to be applied; higher values would give a softer image. Beta value is the threshold value with which the block is first compared before it is deblocked.

Closing Notes

Well, thats all there is to encoding videos using Handbrake. Always make it a practise to encode a preview first and try playing it on your intended device. Video encoding does take a lot of time, and you wouldn’t want to be that fool who spends hours encoding the entire video just to find that it doesn’t work on your device.

Apart from that, have fun encoding! Hope you found this tutorial helpful.

The post Handbrake Tutorial Part 2: x264 Advanced Encoding & Compression Settings Guide appeared first on OCFreaks!.

Quite often you might have come across a pair of earphones that is incompatible with your device. But why is this so, even when the plug fits perfectly in the socket? Buying new earphones is a ritual that most of us have to go through once in a few months or so. Choosing the right pair of buds is a hard enough affair as it is, and such problems simply add to our woes. With this guide, you’ll come to know the reason for these incompatibilities, how you can choose the correct earphone when buying online and how you could (possibly) make incompatible earphones work on your device.

The 3.5mm Earphone Connector (aka Audio Jack)

Most modern phones come with 3.5 mm sockets, and earphones for these are available in plenty. But this is just half the story. The root of the incompatibility lies in the lack of proper standardisation in the 3.5mm connector.

There are two types of 3.5 mm connectors that could come with stereo earphones:

TRS(Tip-Ring-Sleeve) Connector:

Also known as Three Pin Connector or Three Conductor Connector. These are used when the earphones either don’t come with an inline mic, or when the mic uses a connector separate from that of the Audio Out. PCs and mp3 players commonly use TRS sockets.

TRS Connector

For 3 pin TRS connectors in stereo earphones, the connections are pretty much standard:

TRS Connections

TRRS(Tip-Ring-Ring-Sleeve) Connector:

Also known as Four Pin Connector or Four Conductor Connector. These are used when the Mic and Audio Out are provided in a single connector. Most phones use TRRS connectors as it is quite compact, since it eliminates the need of a separate connector for the Mic.

TRRS Connector

Now, in the case of 4 pin TRRS connectors, there are two differing standards by which connections could be made:

OMTP:

This was the original standard for TRRS connectors developed by Nokia. OMTP sockets could commonly be seen in old Nokia and Samsung Phones and Legacy Xperias.

TRRS OMTP Connections

CTIA:

This is at present, more commonly seen standard than OMTP. CTIA sockets are used in HTC, Samsung, Sony, LG and most other android phones, Lumia and iPhones (well, before 7. A few, ahem, “brilliant” engineers at Apple decided it’d be a great idea to drop the 3.5 mm audio socket and use their proprietary Lightning port as the audio connector. But that’s a completely different story and I wont be rambling much about that here).

TRRS CTIA Connections

OMTP Earphones on a CTIA Socket / CTIA Earphones on an OMTP Socket :

Due to the difference in position of the Ground and Mic contacts, OMTP earphones wont work in CTIA sockets, and vice versa. Now, heres the icing on the cake: Most manufacturers dont specify the standard used in their earphones. Well, isn’t that just great?!?!

One way you could check if a particular earphone is compatible with your device is is by checking the compatibility list. For example; If the Earphone manufacturer says “for iPhones”, then it uses CTIA standard. If the earphones are made for Samsung devices, then again it uses CTIA standard. If the earphones are for Legacy Xperia devices or old Nokia Phones, then it uses OMTP standard.

If you have already purchased earphones that are incompatible with your device, what can I say ? Sucks to be you.

Just Kidding ;-). One way you could possibly make it work is by purchasing an adapter.

OMTP to CTIA/CTIA to OMTP Adapter

Such an adapter can convert an OMTP earphone to CTIA as well as a CTIA earphone to OMTP. These are a bit hard to find for cheap, but are well worth the price if it works.

TRRS Earphones on a TRS Socket / TRS Earphones on a TRRS Socket :

3 pin TRS Earphones should be compatible with devices using 4 pin TRRS sockets, as the Ground pin would be connected to the ground contact of the Socket anyways. The same goes for 4 pin TRRS Earphones on a 3 pin TRS socket.

TRS connector in TRRS socket

TRRS connector in TRS socket

However, if these dont work, or if you get a garbled audio, it would most likely be due to improper contact between the plug and socket conductors.

Improper Contact between TRRS Plug and TRS Socket

As can be seen the contacts in the socket will connect with the insulator when the plug is completely inserted in the socket. Another possibility is that the contact touches two of the pins. This is also the reason why the earphones appear to work when you slightly remove the plug.

To make these work, you could try using an adapter with a TRRS female and TRS male connector (4 pin to 3 pin adapter, for TRRS plug – TRS Socket incompatibility) or with a TRS female and TRRS male connector (3 pin to 4 pin adapter, for TRS plug – TRRS Socket incompatibility), depending on your requirements.

The post 3.5mm Earphone Connector Compatibility Issue appeared first on OCFreaks!.

In this article, I will explain to you about the various video redundancies and why eliminating them is of utmost importance and the first thing programmers tend to focus on when making a codec.

First lets go into what a redundancy is. In simple terms, Redundancy is the amount of useless data that exists in a specific information. “Useless”, here, is an extremely subjective term, and what I actually mean to say is though the data does contribute to the information, the contribution itself is so insignificant that reducing or eliminating it wont have any adverse effects.

Those coming here from my Handbrake Complete Tutorial Part 1: How to Transcode & Compress Videos article might remember how most video codecs process each frame of the video in terms of macroblocks. Basically, there are four kinds of redundancies that could exist in a lossless raw video:

1. Spatial Redundancies: Spatial Video Redundancies are the similarities between the surrounding macroblocks. For example, consider the frame shown below:
Spatial Redundancies: The field and the sky, which makes up most of the frame; have largely monotonous hues.
2. Temporal Redundancies: Temporal Video Redundancies are the similarities in successive frames. For example, consider the frames shown below:
[FRAME: 1]
[FRAME: 2]
[FRAME: 3]
[FRAME: 4]
Temporal Redundancies: In these frames, only the car is moving. The rest of the frame(the background) is stationary. So, there is no need to transmit this information in all the frames.
3. Psychovisual Redundancies: Psychovisual Video Redundancies exist due to the fact that the human eye is not equally sensitive to all visual information. So by eliminating the parts to which the eye is less sensitive, the frame can be compressed without a much noticeable quality loss.
4. Coding Redundancies: In an uncompressed raw video, each pixel in a frame is usually encoded to a fixed length. This results in a file that would be much bigger than what is actually required, as the same length is used for each pixel in all the frames, regardless of whether it is required or not. This is called coding redundancy, and can be eliminated by using Variable Length Coding schemes. To see (albeit a crude example) how coding redundancies can be reduced, consider an 8bit 5x5px greyscale image, with the grey levels of the series of pixels going as;
    
   120, 120, 120, 120, 120, 119, 119, 119, 119, 119, 118, 118, 118, 118, 117, 117, 117, 115, 115, 115
    
   This could be represented as is, in which case a total of 160 bits would be required. Or, it could be represented much more efficiently as follows:
    
   5.120, 5.119, 4.118, 3.117, 3.115
    
   This is the basic principle of Run Length Encoding (RLE), one of the oldest and simplest encoding schemes.

How these redundancies are processed and eliminated is one of the defining factors of a Codecs overall efficiency and performance.

Eliminating redundancies is extremely important, especially in the case of videos. This is because of the ridiculously high amount of redundant data that can exist in it. Consider a scenario where you have 86400 images averaging 350 KB per image(really not an inconceivable size for an image of that resolution). A 24fps video made out of that many images would be of around 3GB (for 30 mins). Let that sink in. Also in videos, you really wont see much of a difference between consecutive frames. So, all that data being used to represent it is, as I stated above, “Useless”!

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LGA1156 Platform was released way back in 2009 just 1 year after the release of LGA1366 Platform.

The main differences between lga1156 and lga1366 are as follows:

1. Elimination of northbridge in lga 1156.
2. Only dual channel memory support.
3. Better turbo mode on lga1156.
4. Lower tdp of i7’s on lga1156(95watt opposed to 130 watt in 1366).

This the list of cpu’s that belong to this platform

Core i3(Clarkdale)Dual cores with ht but no turbo:

• -i3 530
• -i3 540

Core i5(Clarkdale) Dual cores with HT and turbo:

• -i5 650
• -i5 660
• -i5 661
• -i5 670

Core i5(Lynfield) Quad cores with turbo but no HT:

• -i5 750
• -i5 750

Core i7(Lynfield) Quad cores with ht and turbo:

• -i7 860
• -i7 870
• -i7 875k
• -i7 880

The chipsets supported are:

• P55–Mainly for core i7 and i5 lynfield versions,although you could run i3 and other i5’s too but you won’t be able to utilize the on cpu graphics unit.
• H55–Mainly for non lynfield i5’s and i3’s as it supports on cpu graphics unit.
• Two More chipsets are available but they are not much different,H57 and Q57.

This concludes the intro.

Setting Up Your System

1. Goto bios(Press F10/Del/F2 at startup) and set everything at default then restart your pc.
2. Again goto bios and disable all power saving features,c-states etc ,.. then set all voltages from auto to normal in the bios except the PCH(discussed later), save settings and exit bios.
3. Disable or remove any unnecessary usb devices PNP devices that you don’t need.
4. Make sure you have adequate cooling and a good cpu cooler(advisable for system safety not mandatory).
5. Make sure you have a good cpu cooler installed before going for heavy overclocking(Eg. cooler master hyper 212+ evo)

Softwares/Utilities Required

1) Core Temp–Used to measure CPU temps.

http://www.alcpu.com/CoreTemp/

2) HWMonitor–This gives temp and voltage info for the whole system including motherboard PCH temp.

http://www.cpuid.com/softwares/hwmonitor.html

3) CPU-Z–Used for getting memory and cpu specific detailed info.

http://www.cpuid.com/softwares/cpu-z.html

4) Prime95–A time tested and very good stability tester for cpu’s of any make and brand.

http://www.overclock.net/t/137251/prime95

5) IBT(Intel Burn Test)–Includes linpack test which is apparently used by intel too for testing the processors.

This is better than Prime 95 as it takes much less time to find stability issues in the system.

http://downloads.guru3d.com/IntelBur…load-2047.html

6) MEMTEST86+–Used to test the memory stability.

http://www.memtest.org/

Well established safe limits–Its better to leave this at auto.(This setting can easily damage your board and components and do very less for ocing so its better left on at auto,sometimes when ocing beyond 4ghz+ and if your cpu is not stable this might help,no guarantees though).

1) Don’t set a target in mind,ocing is a recursive process,there is no guarantee you will achieve your desired overclock.

2) If you know your mother board is weak then don’t take the bclk too high,rather increase CPU multiplier as much as you can to achieve the desired overclock.

3) If you know your mother board can take the heat then its always better for stability reasons to decrease your CPU multiplier as low as you can and increase the bclk to achieve ocing.

4) Before increasing the bclk set the CPU multiplier as low as possible and set the PCI frequency as auto.

5) Decrease the memory multiplier before hand too because when you start ocing through bclk every other clocks/frequencies in the system will also rise.

Finally Overclocking

1) After reading the previously mentioned rules and setting up the bios multipliers and frequencies, goto Bios and start increasing bclk in steps of 5 or 10(if you are confident).Save settings then again enter bios.

2) Now after reentering bios check 3 frequencies every time you increase the bclk:

1. CPU Frequency.
2. Memory Frequency.
3. PCI Frequency(although it is set to auto,doesn’t hurt to check for yourself to be extra sure).

If everything is fine then move on to next step.

3) Save bios settings and exit then boot up windows,start cpuz and core temp and hwmonitor,let them run in the background.

4) Start Prime95 or IBT whichever you trust or like(imo ibt/linx are better):

1. Run it for at least 6 hours and check for errors or bsod’s or any decripency in system behaviour.
2. If you get any error/bsod then you might need to review your bios setting and try increasing vcore/qpi voltage a bit.
3. If you did not get any error then congratulations you have done your first successfull overclock.

1. Set the run times to 20(even 10 will do,but to be extra sure),and run it and then see for any errors bsod’s and any decripency in system behaviour.
2. If you get any error/bsod then you might need to review your bios setting and try increasing vcore/qpi voltage a bit.
3. If you did not get any error then congratulations you have done your first successfull overclock.

5) Do steps 1-4 again and again till you stabilize the system(keeping voltage under safe range as stated by me in voltage section) and achieve your desired overclock.

6) In case your pc stops booting reset cmos by removing the battery in the motherboard and keep it out for 5 minutes and then put it back in and reboot.If your system still does not start it means something has gone kaput.

7) If you encounter step 6,its highly likely that either your power supply or motherboard were not upto the task or you have been overenthusiastic and pushed your system too hard.

This concludes ocing section.

End Notes

This concludes the guide.

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Legacy Intel LGA 775 Overclocking

Basically Front Side Bus (FSB) is set of wires i.e. a Bus that connects CPU to the “Northbridge(Chipset)”.By the way – Intel also calls the Northbridge as “Memory Controller Hub” or MCH for short.

Wait … what is the Northbridge in the first place?

Now back to where I was …

This FSB is the address and data bus which the CPU uses. The CPU interacts with all the other components of the computer through the FSB via the Northbridge. Since the Northbridge is so central to all the connections in the computer – increasing the FSB will also increase the speed at which other components interact with the Northbridge which in turn will increase the system performance. Overclocking the FSB may be a little tricky for someone new because the base clock rate differs from the effective(actual) clock rate which is termed as ‘Quad-Pumping’ by Intel.

On systems that support Intel processors the FSB is Quad Pumped which can be stated as :

Hence for eg. a system running at 1333 MHz FSB has a base FSB frequency of 333 MHz.

One of the key factors that makes FSB the first choice to be overclocked is that the CPU’s speed is determined by the Base FSB which is then multiplied by the CPU Multiplier which sets the operating frequency of the CPU.This relation of proportionality between the CPU and FSB frequency gives an instant CPU speed boost when the FSB is increased given that the multiplier remains the same.

The formula is given as :

The CPU multiplier is also referred to as CPU to FSB ratio in some BIOSes – its logical because if you divide CPU frequency with FSB freq what we get is the CPU Multiplier.

Lets take an example of Q9300 which has native FSB of 1333 MHz (Quad Pumped) and Multiplier ‘Top-Locked’ to 7.5

Native Processor FSB is the default FSB which is used to generate the CPU frequency. Each processor has its own predefined default FSB. When every thing is set to default – i.e. no Overclocking – the CPU dictates the Northbrigde that it wants to work at the default CPU FSB.

When is comes to FSB we are mainly concerned with max FSB supported by the motherboard and the native FSB of the processor. The Q9xx0 series Quads from Intel may have the edge of being 45nm based and slightly faster than the 65nm based Q6×00 series Quads. But the 45nm Quads have higher native FSB of 1333 MHz which makes it difficult to overclock beyond a limit and it even gets worse for quads like Q9300 which has the multiplier at 7.5 max. Consider today’s p35 , x38 , p45 , x48 chipset based motherboards which can be OCed to 1600MHz easily but not quite beyond 2000 MHz i.e. a Base FSB of 500 MHz is limit for the current generation chipsets. Now with Q9300 the ‘max possible (can be pushed more)’ overclock will be = 500 x 7.5 = 3.75 GHz which does not make it suitable for Overclocking because such a high FSB will tax both the chipset and also the RAM to maintain good FSB : DRAM ratios [ill explain RAM OCing in next Article].

On the other hand lets consider Q6600 which has 1066MHz with multiplier of 9 max. With Q6600 the ‘max possible’ OC will be = 500 x 9 = 4.5 GHz which some have reached. I remember that the Tom’s Hardware team from France managed to push Q6600 up to 5 GHz on liquid nitrogen. Due to this relation between the Base FSB and the CPU Multiplier the CPU having native FSB less then the max FSB supported by the motherboard has a more Overclocking head room than a CPU have native FSB same as the max FSB of the motherboard.

In our consideration of Q9300 and Q6600 I would go with Q6600 because its more Overclockable and will not tax the chipset with extreme high FSB as with Q9300. But on the other side the main advantage of Q9300 is the higher FSB itself. Since the native FSB of the processor dictates the default FSB at which the system will run having higher default FSB will make system run fast due to higher FSB. But the down fall is that further OC is possible from the default FSB , hence more the head room more is the Overclockability.

AMD With HTT

On AMD systems the bus used to interface the CPU with Northbridge uses HyperTransport Technology (HTT) which was earlier called Lighting Data Transport (LDT). This is similar to FSB on Intel systems which uses Assisted/Advanced Gunning Transreceiver Logic (AGTL+). On AMD systems the bus speed is the base HT speed from which we get the HT Link speed.

Here’s the formula :

Usually the HT multiplier swing is limited between 1 and 5(max).
So if we have bus speed of 200 MHz and HT multiplier set to 5x then our HT link speed will be : 200 x 5 = 1000 MHz HT Link

The HT link speed is used to get actual data rate of the system bus. Since HTT can transfer data twice per clock pulse (Double Data Rate) the effective can be calculated as :

In our case we have: 1000 MHz x 2 = 2000 MHz Effective Bus Data Rate

As on Intel systems the CPU speed here is also obtained by multiplying the CPU Multiplier with the bus speed (Base HT) which is as follows :

Lets say we have an AMD X2 5000+ which has its multiplier set to 13 . Hence in our case the CPU would be : 200 x 13 = 2600 MHz = 2.6 GHz

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